NEWS & INSIGHTS

Company News and Technology Updates

Company progress, product milestones and technical articles, maintained from one content source and ready for the English site.

09/24/2026Technology

Why edge LLM inference needs a dataflow-driven GPNPU

The key edge constraints are weight capacity, effective bandwidth and fast model evolution. A GPNPU co-designs compute, interconnect and software around the real inference dataflow.

Token generation repeatedly accesses model weights. Instead of adding peak compute alone, edge systems need effective bandwidth, low-bit formats, sparse-model support and software usability. VELOXIS AI combines FusionCore, ScaleNoC and TileFlow into a dataflow-driven GPNPU architecture for dense models, sparse MoE and multi-agent workloads.

09/24/2026Product

Qwen-8B completes end-to-end validation on the FPGA prototype

The team completed end-to-end Qwen-8B validation on the FPGA prototype, covering compute, interconnect, compiler scheduling and software integration.

The validation covered model loading, operator execution, on-chip data movement and runtime scheduling. It provides an engineering foundation for chip integration and future silicon validation. Results are from an FPGA prototype, not production silicon.

09/14/2026Company

VELOXIS AI closes a tens-of-millions RMB angel round

The company has completed a tens-of-millions RMB angel round. Proceeds will support first-chip tape-out, engineering validation and core R&D hiring.

The round was led by the Guoxin Zhongshu Tongling Science and Innovation Fund. Proceeds will primarily support first-chip tape-out, engineering validation and core R&D team building.

07/16/2026Company

Hangzhou VELOXIS AI was founded

The company was founded to build an edge GPNPU architecture, accelerator cards, and AI compute and interconnect IP.

Hangzhou VELOXIS AI was founded under the English brand VELOXIS AI. The company develops an edge GPNPU architecture and advances AI compute and interconnect IP.