NPU architecture & algorithms
Compute arrays, dataflow, tiling, memory hierarchy, performance modeling and algorithm co-design.
- NPU architecture / microarchitecture
- AI chip algorithms / HW-SW co-design
- Intern: NPU architecture / algorithm co-design
BUILD AT THE EDGE
We are building a core team across NPU architecture, RTL, verification, compiler, runtime, performance modeling, implementation and prototyping.
OPEN ROLES
Location: Hangzhou. Internships are onsite-first with partial remote collaboration possible; submit your resume, project materials or GitHub link through our online form.
Compute arrays, dataflow, tiling, memory hierarchy, performance modeling and algorithm co-design.
RTL and microarchitecture for NPU, SoC, NoC, memory systems and high-speed interfaces.
Module and subsystem functional verification, performance validation, verification environments and automation.
Graph/IR, operator fusion, runtime, driver, firmware and model deployment pipelines.
Functional/performance models, cycle simulators, workload analysis and design-space exploration.
Implementation from synthesis, STA and P&R to DFT, FPGA prototype and emulation.
RECRUITMENT MATERIALS
Materials for campus, experienced and offline recruiting. View or download directly.
APPLY
Apply through the Feishu online form. If the form is unavailable, email careers@veloxis-tech.com.
ONLINE APPLICATION
Submit your resume, project materials or GitHub link through our Feishu form. We will contact you by email or Feishu after review.
Open application formIf the form does not open, email careers@veloxis-tech.com with the subject “Role + Name”.