COMPUTE + INTERCONNECT IP

Turn compute, interconnect and software into integrable IP subsystems.

Provides FusionCore compute IP, ScaleNoC interconnect IP, subsystems and custom design services to chip, SoC and accelerator teams.

IP PORTFOLIO

License separately or deliver as a combined subsystem.

License scope, deliverables, acceptance and payment terms are project-specific; compute scale, precision and interfaces are configured to customer requirements.

COMPUTE

FusionCore Compute IP

A compute core for LLM inference, combining matrix compute, vector processing and on-chip memory, with precision and scale configured per workload.

Multi-precision compute and block scaling
Matrix, vector and special-function paths
Available as compute IP or a compute subsystem

INTERCONNECT

ScaleNoC Interconnect IP

Connects multiple compute cores, on-chip memory and external interfaces with dataflow-configurable topology and link bandwidth.

Available standalone or combined with FusionCore
For multi-core and shared-memory architectures
Supports system integration and validation

Requirements

Define architecture boundaries from models, precision, compute scale, memory system and interface constraints.

Integration & adaptation

Adapt and integrate compute IP, interconnect, software interfaces and the target system.

Validation & delivery

Complete validation, version delivery, acceptance and support by project agreement.

IP ARCHITECTURE

Compute and interconnect can be integrated separately.

FusionCore and ScaleNoC can be licensed as separate modules or combined into a compute subsystem, configured for the customer model, precision, interface and system scale.

FusionCore compute IP architecture — FusionCore multi-precision compute IP

ScaleNoC interconnect IP architecture — ScaleNoC on-chip interconnect IP

FROM IP TO PRODUCT

One architecture connects IP delivery and standard products.

Reusable modules, software and validation experience from chip projects feed into the VLX accelerator family.

View VLX products