VLX SERIES
VLX-64 adds edge inference to industrial PCs, compute boxes, smart terminals and robots as an accelerator or engineering module, without replacing the existing CPU, OS or applications.
The first-generation edge accelerator targets mainstream edge models and sparse MoE evaluation, available in M.2 and USB engineering-module formats.
A future roadmap for workstations and larger edge systems, planned as a PCIe accelerator and a local inference terminal.
The information above includes design targets and roadmap items, not silicon measurements. Interfaces, power, software compatibility and performance are subject to the official engineering release.
FORM FACTORS
The first product phase covers M.2 and USB engineering modules, expanding later to PCIe cards and local inference terminals.
INTEGRATION
Evaluate integration from host interfaces and drivers to model adaptation and runtime based on real devices and workloads.
Keep the CPU, OS, business applications and device control.
Integrate based on interface, power, thermal and space constraints.
Adapt models, quantization, operator compilation and runtime.
Evaluate throughput, latency and deployment with real tasks.
START A CONVERSATION
Share the target device, model scale, interfaces and deployment constraints; the team will define the product configuration and integration path.
